Phase locked loops 6 e design simulation and applications pdf
McGraw-Hill - Phase-Locked Loops Design , Simulation and Applications 5.Ed
It seems that you're in Germany. We have a dedicated site for Germany. This book presents a novel approach to the analysis and design of all-digital phase-locked loops ADPLLs , technology widely used in wireless communication devices. Realistic examples illustrate how to analyze and simulate phase noise in the presence of sigma-delta modulation and time-to-digital conversion. Analytical and simulation tools are discussed in detail. Matlab code is included that can be reused to design, simulate and analyze the ADPLL architectures that are presented in the book.
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A phase-locked loop or phase lock loop PLL is a control system that generates an output signal whose phase is related to the phase of an input signal. There are several different types; the simplest is an electronic circuit consisting of a variable frequency oscillator and a phase detector in a feedback loop. The oscillator generates a periodic signal, and the phase detector compares the phase of that signal with the phase of the input periodic signal, adjusting the oscillator to keep the phases matched. Keeping the input and output phase in lock step also implies keeping the input and output frequencies the same. Consequently, in addition to synchronizing signals, a phase-locked loop can track an input frequency, or it can generate a frequency that is a multiple of the input frequency.
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